Interconnection Crossbar

A interconnection scheme
    used by distributed memory multiprocessors

This two-dimensional array of switches
    connects the processors and memory units
        permitting dynamic configurations

As can be seen from the diagram
    there are many paths from one processor
        to another

And all processors have access to all memories
    as well as to each other

There are n memory modules
    times n processors

This means that O(n²) switches
    are required   (expensive)

Thus, the scalability is limited
    by the number of switches that is affordable

Examples:

• Intel Paragon

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Comments:
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