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Computer
Science Department Colloquium Pushing the limits of hardware acceleration Speaker: Steven Derrien, Professor, Joint EE/CS department, University of Rennes 1, France When: 11:00AM ~ 11:50AM, February 4, 2019 Where: CSB130 Abstract: FPGA and ASIC hardware accelerators are now finding their way into datacenters and cloud computing architectures. Such devices significantly outperform CPUs and GPUs for many workloads, either from the performance or energy efficiency point of view. However, designing such accelerators is a challenge, as standard methodologies and tools operate at low levels of abstractions (gate/register level). Because of this, designing accelerators remains out of reach for (most) software developers, and their use is often restricted to “simple” applications and/or kernels. A lot of research has gone developing High-Level-Synthesis tools, which act as C to hardware compilers, and aim at offering “software like” abstractions to designers. Although there now exist mature commercial tools, many designers are still reluctant to switch to these tools, as they do not clearly see how far they can be pushed. In this talk, I will try to (partly) answer this question through two use cases: The first one shows how low level circuit optimizations technique can be reformulated in the context of HLS tools. The second one will show that the productivity improvement offered by HLS tools open new perspective for research in computer architecture. Bio: Steven Derrien is a professor in the joint EE/CS departement at University of Rennes 1 in France. He is also a member of the CAIRN research group at IRISA/INRIA. His research interests revolve around High Level Synthesis of non programmable hardware accelerators and hardware design in general. |