DBT-2003 :   IEEE INTERNATIONAL WORKSHOP

                                                                                            ON

            CURRENT & DEFECT BASED TESTING

            April 27, 2003  Napa Valley Marriott, Napa Valley, CA, USA

Held in conjunction with      IEEE VLSI Test Symposium (VTS-03)

GENERAL CHAIR

Hank Walker

Texas A&M University, USA

VICE GENERAL CHAIR

Adit Singh

Auburn University, USA

PROGRAM Co CHAIRs

Hans Manhaeve

Q-Star Test nv Brugge, Belgium

James Plusquellic

Univ. of Maryland, Baltimore County

LOCAL ARRANGEMENTS
P. Roy
Intel, USA

FINANCE CHAIR
Sankaran M. Menon

Intel Corporation, USA

PUBLICITY CHAIR

Michell Renovell

LIRMM, France

 

ADVISOR

Charles Hawkins 

University of New Mexico, USA

STEERING COMMITTEE

Yashwant K. Malaiya (Chair)

                Colorado State University, USA

Anura  Jayasumana C ol State Univ, USA

Joan Figueras, UPC, Barcelona, Spain

Rochit Rajsuman, Advantest, USA

Kozo Kinoshita, Osaka University, Japan

PROGRAM COMMITTEE

Robert Aitken, Agilent Technologies, USA

Waleed Al-Assadi, IBM, USA

Tom  Barnett, Auburn University, USA

Sreejit Chakravarty, Intel, USA

Anne Gattiker, IBM, USA

Sri Jandhyala, Texas Instruments, USA

Ali Keshavarzi, Intel, USA

Kozo Kinoshita, Osaka University, Japan

Bram Kruseman, Philips, The Netherlands

Peter Maxwell, Agilent Technologies, USA
Ed McCluskey, Stanford Univ., USA

Michel Renovell, LIRMM, France

Andrew Richardson, Lancaster Univ., UK
Marly Roncken, Intel, USA

Rob Roy, Mobilian, USA

Manoj Sachdev, Univ. of Waterloo, Canada
Jaume Segura, UIB, Balears, Spain

Jerry Soden, Sandia National Labs, USA

Claude Thibeault,Ecole de Tech Sup,Canada
Duncan (Hank) Walker, Texas A&M Univ.

Victor Zieren, Philips Res., The Netherlands

CALL FOR PAPERS AND PARTICIPATION

Defect Based Testing in Nanometer Technologies

The new and varied failure modes being observed in present generation DSM circuits raise an important question: Can traditional test strategies, built around logical fault models, meet the test challenges in emerging nanometer technologies, or must we increasingly rely on defect based test methods that directly target physical defects? The IEEE International Workshop on Current and Defect Based Testing (DBT 2003) is aimed at addressing this question by providing an informal forum for the discussion of key recent advances and open research issues relating to defect based testing and associated test methodologies.  The theme of this year’s workshop “Defect Based Testing in Nanometer Technologies” has been selected to generate active discussion on the challenges that must be met to ensure high IC product quality through to the end of the decade. 

Representative topics of interest include, but are not limited to, the following:

·         Delay Tests and Opens

·         Shorts and Bridging Defects

·         IDDQ and IDDT Testing

·         Low voltage Testing

·         Elevated Voltage Testing

·         Stress Testing

·         Reliability and Yield

·         Burn In Minimization

·         Noise and Cross-talk Testing

·         Nanometer Test Challenges

·         DSM Defect Mechanisms

·         Technology Trends and Testing

·         Test Generation Tools

·         Mixed Current/Voltage Testing

·         Economics of  Defect Based Testing

·         On and Off Chip Current Sensors

·         Defect Coverage & Metrics

·         Fault Location & Diagnosis

·         IDDQ Limit Setting

·         IDD Testing of Analog/Mixed Circuits

To present at the workshop, submit a postscript or Acrobat (PDF) version of an extended abstract (about 1000 words), as an E-mail attachment, to the program chair by Dec. 13, 2002. Each submission should include full name and address of each author, affiliation, telephone number, FAX and E-mail address. The presenter should also be identified. Camera-ready papers for distribution in the informal proceedings will be due on Feb. 14, 2003. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome.  Proposals for debates and panel discussions are also invited.

AUTHOR’S SCHEDULE:

                        Submission of Extended Abstract:         Dec 13, 2002 Extended to Jan 15, 2002

                        Notification of Acceptance:                   Jan 17, 2003

                        Camera Ready Paper:                           Feb 14, 2003

Technical Program Submissions:                   General Information

Jim Plusquellic                                               Hank Walker

Department of CSEE                                                            Texas A&M University

Univ of Maryland, Baltimore County,                              Dept. of Computer Science   

Tel: (410) 455-1349, Fax: -3969                            College Station, TX 77843, USA

Baltimore, MD 21250, USA                                 Tel: (979) 862-4387, 847-8578 (FAX)

E-mail: plusquel@csee.umbc.edu                                      E-mail: walker@cs.tamu.edu

Visit our www site at: http://www.cs.colostate.edu/~malaiya/dbt.html

                                                              

 

Sponsored by: IEEE Computer Society Test Technology Technical Committee