Interconnection Bus

A simple, static interconnection scheme
    used by early shared memory multiprocessors

There can be a single large shared memory
    or there can be a number of shared memory units

The bus is shared by all the attached processors
    and memories

All data transmissions occur on the bus

No routing is required,
    as all communication goes to all nodes and memories

This means that the bus
    can become a bottleneck

The scalability of this scheme
    is limited by the bandwidth of the bus

Examples:

• Encore Multimax
• Sequent Balance
• Sequent Symmetry

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Comments:
Copyright © 2001-2003: Colorado State University for CS 551. All rights reserved.

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